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00001 #ifndef __ARMV7_P15_H__ 00002 #define __ARMV7_P15_H__ 00003 #include "arch_types.h" 00004 00005 00006 /* Generic ARM Registers */ 00007 #define read_cpsr() ({ uint32_t rval; asm volatile(\ 00008 " mrs %0, cpsr\n\t" \ 00009 : "=r" (rval) : : "memory", "cc"); rval;}) 00010 #define read_vbar() ({ uint32_t rval; asm volatile(\ 00011 " mrc p15, 0, %0, c12, c0, 0\n\t" \ 00012 : "=r" (rval) : : "memory", "cc"); rval;}) 00013 #define write_vbar(val) asm volatile(\ 00014 " mcr p15, 0, %0, c12, c0, 0\n\t" \ 00015 :: "r" ((val)) : "memory", "cc") 00016 00017 /* ARMv7 Registers */ 00018 #define HCR_FMO 0x8 00019 #define HCR_IMO 0x10 00020 #define HCR_VI (0x1 << 7) 00021 00022 /* 32bit case only */ 00023 #define read_ttbr0() ({ uint32_t rval; asm volatile(\ 00024 " mrc p15, 0, %0, c2, c0, 0\n\t" \ 00025 : "=r" (rval) : : "memory", "cc"); rval;}) 00026 00027 #define write_ttbr0(val) asm volatile(\ 00028 " mcr p15, 0, %0, c2, c0, 0\n\t" \ 00029 :: "r" ((val)) : "memory", "cc") 00030 00031 #define read_ttbr1() ({ uint32_t rval; asm volatile(\ 00032 " mrc p15, 0, %0, c2, c0, 1\n\t" \ 00033 : "=r" (rval) : : "memory", "cc"); rval;}) 00034 00035 #define write_ttbr1(val) asm volatile(\ 00036 " mcr p15, 0, %0, c2, c0, 1\n\t" \ 00037 :: "r" ((val)) : "memory", "cc") 00038 00039 #define read_ttbcr() ({ uint32_t rval; asm volatile(\ 00040 " mrc p15, 0, %0, c2, c0, 2\n\t" \ 00041 : "=r" (rval) : : "memory", "cc"); rval;}) 00042 00043 #define write_ttbcr(val) asm volatile(\ 00044 " mcr p15, 0, %0, c2, c0, 2\n\t" \ 00045 :: "r" ((val)) : "memory", "cc") 00046 00047 #define read_mair0() ({ uint32_t rval; asm volatile(\ 00048 " mrc p15, 4, %0, c10, c2, 0\n\t" \ 00049 : "=r" (rval) : : "memory", "cc"); rval;}) 00050 00051 #define write_mair0(val) asm volatile(\ 00052 " mcr p15, 4, %0, c10, c2, 0\n\t" \ 00053 :: "r" ((val)) : "memory", "cc") 00054 00055 #define read_mair1() ({ uint32_t rval; asm volatile(\ 00056 " mrc p15, 4, %0, c10, c2, 1\n\t" \ 00057 : "=r" (rval) : : "memory", "cc"); rval;}) 00058 00059 #define write_mair1(val) asm volatile(\ 00060 " mcr p15, 4, %0, c10, c2, 1\n\t" \ 00061 :: "r" ((val)) : "memory", "cc") 00062 00063 #define read_hmair0() ({ uint32_t rval; asm volatile(\ 00064 " mrc p15, 4, %0, c10, c2, 0\n\t" \ 00065 : "=r" (rval) : : "memory", "cc"); rval;}) 00066 00067 #define write_hmair0(val) asm volatile(\ 00068 " mcr p15, 4, %0, c10, c2, 0\n\t" \ 00069 :: "r" ((val)) : "memory", "cc") 00070 00071 #define read_hmair1() ({ uint32_t rval; asm volatile(\ 00072 " mrc p15, 4, %0, c10, c2, 1\n\t" \ 00073 : "=r" (rval) : : "memory", "cc"); rval;}) 00074 00075 #define write_hmair1(val) asm volatile(\ 00076 " mcr p15, 4, %0, c10, c2, 1\n\t" \ 00077 :: "r" ((val)) : "memory", "cc") 00078 00079 #define read_hsr() ({ uint32_t rval; asm volatile(\ 00080 " mrc p15, 4, %0, c5, c2, 0\n\t" \ 00081 : "=r" (rval) : : "memory", "cc"); rval;}) 00082 #define read_htcr() ({ uint32_t rval; asm volatile(\ 00083 " mrc p15, 4, %0, c2, c0, 2\n\t" \ 00084 : "=r" (rval) : : "memory", "cc"); rval;}) 00085 00086 #define write_htcr(val) asm volatile(\ 00087 " mcr p15, 4, %0, c2, c0, 2\n\t" \ 00088 :: "r" ((val)) : "memory", "cc") 00089 00090 #define read_hsctlr() ({ uint32_t rval; asm volatile(\ 00091 " mrc p15, 4, %0, c1, c0, 0\n\t" \ 00092 : "=r" (rval) : : "memory", "cc"); rval;}) 00093 00094 #define write_hsctlr(val) asm volatile(\ 00095 " mcr p15, 4, %0, c1, c0, 0\n\t" \ 00096 :: "r" ((val)) : "memory", "cc") 00097 00098 #define read_sctlr() ({ uint32_t rval; asm volatile(\ 00099 " mrc p15, 0, %0, c1, c0, 0\n\t" \ 00100 : "=r" (rval) : : "memory", "cc"); rval;}) 00101 00102 #define write_sctlr(val) asm volatile(\ 00103 " mcr p15, 0, %0, c1, c0, 0\n\t" \ 00104 :: "r" ((val)) : "memory", "cc") 00105 00106 #define read_httbr() ({ uint32_t v1, v2; asm volatile(\ 00107 " mrrc p15, 4, %0, %1, c2\n\t" \ 00108 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00109 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00110 00111 #define write_httbr(val) asm volatile(\ 00112 " mcrr p15, 4, %0, %1, c2\n\t" \ 00113 :: "r" ((val) & 0xFFFFFFFF), "r" ((val) >> 32) \ 00114 : "memory", "cc") 00115 00116 #define read_vtcr() ({ uint32_t rval; asm volatile(\ 00117 " mrc p15, 4, %0, c2, c1, 2\n\t" \ 00118 : "=r" (rval) : : "memory", "cc"); rval;}) 00119 00120 #define write_vtcr(val) asm volatile(\ 00121 " mcr p15, 4, %0, c2, c1, 2\n\t" \ 00122 :: "r" ((val)) : "memory", "cc") 00123 00124 #define read_vttbr() ({ uint32_t v1, v2; asm volatile(\ 00125 " mrrc p15, 6, %0, %1, c2\n\t" \ 00126 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00127 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00128 00129 #define write_vttbr(val) asm volatile(\ 00130 " mcrr p15, 6, %0, %1, c2\n\t" \ 00131 :: "r" ((val) & 0xFFFFFFFF), "r" ((val) >> 32) \ 00132 : "memory", "cc") 00133 00134 #define read_hcr() ({ uint32_t rval; asm volatile(\ 00135 " mrc p15, 4, %0, c1, c1, 0\n\t" \ 00136 : "=r" (rval) : : "memory", "cc"); rval;}) 00137 00138 #define write_hcr(val) asm volatile(\ 00139 " mcr p15, 4, %0, c1, c1, 0\n\t" \ 00140 :: "r" ((val)) : "memory", "cc") 00141 00142 #define read_midr() ({ uint32_t rval; asm volatile(\ 00143 " mrc p15, 0, %0, c0, c0, 0\n\t" \ 00144 : "=r" (rval) : : "memory", "cc"); rval;}) 00145 00146 #define read_mpidr() ({ uint32_t rval; asm volatile(\ 00147 " mrc p15, 0, %0, c0, c0, 5\n\t" \ 00148 : "=r" (rval) : : "memory", "cc"); rval;}) 00149 00150 /* Generic Timer */ 00151 00152 #define read_cntfrq() ({ uint32_t rval; asm volatile(\ 00153 " mrc p15, 0, %0, c14, c0, 0\n\t" \ 00154 : "=r" (rval) : : "memory", "cc"); rval;}) 00155 00156 #define write_cntfrq(val) asm volatile(\ 00157 " mcr p15, 0, %0, c14, c0, 0\n\t" \ 00158 :: "r" ((val)) : "memory", "cc") 00159 00160 #define read_cnthctl() ({ uint32_t rval; asm volatile(\ 00161 " mrc p15, 4, %0, c14, c1, 0\n\t" \ 00162 : "=r" (rval) : : "memory", "cc"); rval;}) 00163 00164 #define write_cnthctl(val) asm volatile(\ 00165 " mcr p15, 4, %0, c14, c1, 0\n\t" \ 00166 :: "r" ((val)) : "memory", "cc") 00167 00168 #define read_cnthp_ctl() ({ uint32_t rval; asm volatile(\ 00169 " mrc p15, 4, %0, c14, c2, 1\n\t" \ 00170 : "=r" (rval) : : "memory", "cc"); rval;}) 00171 00172 #define write_cnthp_ctl(val) asm volatile(\ 00173 " mcr p15, 4, %0, c14, c2, 1\n\t" \ 00174 :: "r" ((val)) : "memory", "cc") 00175 00176 #define read_cnthp_cval() ({ uint32_t v1, v2; asm volatile(\ 00177 " mrrc p15, 6, %0, %1, c14\n\t" \ 00178 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00179 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00180 00181 #define write_cnthp_cval(val) asm volatile(\ 00182 " mcrr p15, 6, %0, %1, c14\n\t" \ 00183 :: "r" ((val) & 0xFFFFFFFF), "r" ((val) >> 32) \ 00184 : "memory", "cc") 00185 00186 #define read_cnthp_tval() ({ uint32_t rval; asm volatile(\ 00187 " mrc p15, 4, %0, c14, c2, 0\n\t" \ 00188 : "=r" (rval) : : "memory", "cc"); rval;}) 00189 00190 #define write_cnthp_tval(val) asm volatile(\ 00191 " mcr p15, 4, %0, c14, c2, 0\n\t" \ 00192 :: "r" ((val)) : "memory", "cc") 00193 00194 #define read_cntkctl() ({ uint32_t rval; asm volatile(\ 00195 " mrc p15, 0, %0, c14, c1, 0\n\t" \ 00196 : "=r" (rval) : : "memory", "cc"); rval;}) 00197 00198 #define write_cntkctl(val) asm volatile(\ 00199 " mcr p15, 0, %0, c14, c1, 0\n\t" \ 00200 :: "r" ((val)) : "memory", "cc") 00201 00202 #define read_cntp_ctl() ({ uint32_t rval; asm volatile(\ 00203 " mrc p15, 0, %0, c14, c2, 1\n\t" \ 00204 : "=r" (rval) : : "memory", "cc"); rval;}) 00205 00206 #define write_cntp_ctl(val) asm volatile(\ 00207 " mcr p15, 0, %0, c14, c2, 1\n\t" \ 00208 :: "r" ((val)) : "memory", "cc") 00209 00210 #define read_cntp_cval() ({ uint32_t v1, v2; asm volatile(\ 00211 " mrrc p15, 2, %0, %1, c14\n\t" \ 00212 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00213 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00214 00215 #define write_cntp_cval(val) asm volatile(\ 00216 " mcrr p15, 2, %0, %1, c14\n\t" \ 00217 :: "r" ((val) & 0xFFFFFFFF), "r" ((val) >> 32) \ 00218 : "memory", "cc") 00219 00220 #define read_cntp_tval() ({ uint32_t rval; asm volatile(\ 00221 " mrc p15, 0, %0, c14, c2, 0\n\t" \ 00222 : "=r" (rval) : : "memory", "cc"); rval;}) 00223 00224 #define write_cntp_tval(val) asm volatile(\ 00225 " mcr p15, 0, %0, c14, c2, 0\n\t" \ 00226 :: "r" ((val)) : "memory", "cc") 00227 00228 #define read_cntpct() ({ uint32_t v1, v2; asm volatile(\ 00229 " mrrc p15, 0, %0, %1, c14\n\t" \ 00230 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00231 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00232 00233 #define read_cntv_ctl() ({ uint32_t rval; asm volatile(\ 00234 " mrc p15, 0, %0, c14, c3, 1\n\t" \ 00235 : "=r" (rval) : : "memory", "cc"); rval;}) 00236 00237 #define write_cntv_ctl(val) asm volatile(\ 00238 " mcr p15, 0, %0, c14, c3, 1\n\t" \ 00239 :: "r" ((val)) : "memory", "cc") 00240 00241 #define read_cntv_cval() ({ uint32_t v1, v2; asm volatile(\ 00242 " mrrc p15, 3, %0, %1, c14\n\t" \ 00243 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00244 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00245 00246 #define write_cntv_cval(val) asm volatile(\ 00247 " mcrr p15, 3, %0, %1, c14\n\t" \ 00248 :: "r" ((val) & 0xFFFFFFFF), "r" ((val) >> 32) \ 00249 : "memory", "cc") 00250 00251 #define read_cntv_tval() ({ uint32_t rval; asm volatile(\ 00252 " mrc p15, 0, %0, c14, c3, 0\n\t" \ 00253 : "=r" (rval) : : "memory", "cc"); rval;}) 00254 00255 #define write_cntv_tval(val) asm volatile(\ 00256 " mcr p15, 0, %0, c14, c3, 0\n\t" \ 00257 :: "r" ((val)) : "memory", "cc") 00258 00259 #define read_cntvct() ({ uint32_t v1, v2; asm volatile(\ 00260 " mrrc p15, 1, %0, %1, c14\n\t" \ 00261 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00262 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00263 00264 #define read_cntvoff() ({ uint32_t v1, v2; asm volatile(\ 00265 " mrrc p15, 4, %0, %1, c14\n\t" \ 00266 : "=r" (v1), "=r" (v2) : : "memory", "cc"); \ 00267 (((uint64_t)v2 << 32) + (uint64_t)v1);}) 00268 00269 #define write_cntvoff(val) asm volatile(\ 00270 " mcrr p15, 4, %0, %1, c14\n\t" \ 00271 :: "r" ((val) & 0xFFFFFFFF), "r" ((val) >> 32) \ 00272 : "memory", "cc") 00273 00274 #define read_hdfar() ({ uint32_t rval; asm volatile(\ 00275 " mrc p15, 4, %0, c6, c0, 0\n\t" \ 00276 : "=r" (rval) : : "memory", "cc"); rval;}) 00277 00278 #define write_hdfar(val) asm volatile(\ 00279 " mcr p15, 4, %0, c6, c0, 0\n\t" \ 00280 :: "r" ((val)) : "memory", "cc") 00281 00282 #define read_hifar() ({ uint32_t rval; asm volatile(\ 00283 " mrc p15, 4, %0, c6, c0, 2\n\t" \ 00284 : "=r" (rval) : : "memory", "cc"); rval;}) 00285 00286 #define write_hifar(val) asm volatile(\ 00287 " mcr p15, 4, %0, c6, c0, 2\n\t" \ 00288 :: "r" ((val)) : "memory", "cc") 00289 00290 #define read_hpfar() ({ uint32_t rval; asm volatile(\ 00291 " mrc p15, 4, %0, c6, c0, 4\n\t" \ 00292 : "=r" (rval) : : "memory", "cc"); rval;}) 00293 00294 #define write_hpfar(val) asm volatile(\ 00295 " mcr p15, 4, %0, c6, c0, 4\n\t" \ 00296 :: "r" ((val)) : "memory", "cc") 00297 00298 /* TLB maintenance operations */ 00299 00300 /* Invalidate entire unified TLB */ 00301 #define invalidate_unified_tlb(val) asm volatile(\ 00302 " mcr p15, 0, %0, c8, c7, 0\n\t" \ 00303 :: "r" ((val)) : "memory", "cc") 00304 #endif 00305 00306
1.7.6.1
