khypervisor: generic_timer/generic_timer

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00001 #ifndef __GENERIC_TIMER_REGS_H__
00002 #define __GENERIC_TIMER_REGS_H__
00003 #include "asm-arm_inline.h"
00004 #include "armv7_p15.h"
00005 #include "arch_types.h"
00006 
00007 #define GENERIC_TIMER_CTRL_ENABLE       (1 << 0)
00008 #define GENERIC_TIMER_CTRL_IMASK        (1 << 1)
00009 #define GENERIC_TIMER_CTRL_ISTATUS      (1 << 2)
00010 #define generic_timer_pcounter_read()   read_cntpct()
00011 #define generic_timer_vcounter_read()   read_cntvct()
00012 
00013 
00014 enum {
00015     GENERIC_TIMER_REG_FREQ,
00016     GENERIC_TIMER_REG_HCTL,
00017     GENERIC_TIMER_REG_KCTL,
00018     GENERIC_TIMER_REG_HYP_CTRL,
00019     GENERIC_TIMER_REG_HYP_TVAL,
00020     GENERIC_TIMER_REG_HYP_CVAL,
00021     GENERIC_TIMER_REG_PHYS_CTRL,
00022     GENERIC_TIMER_REG_PHYS_TVAL,
00023     GENERIC_TIMER_REG_PHYS_CVAL,
00024     GENERIC_TIMER_REG_VIRT_CTRL,
00025     GENERIC_TIMER_REG_VIRT_TVAL,
00026     GENERIC_TIMER_REG_VIRT_CVAL,
00027     GENERIC_TIMER_REG_VIRT_OFF,
00028 };
00029 
00030 static inline void generic_timer_reg_write(int reg, uint32_t val)
00031 {
00032     switch (reg) {
00033     case GENERIC_TIMER_REG_FREQ:
00034         write_cntfrq(val);
00035         break;
00036     case GENERIC_TIMER_REG_HCTL:
00037         write_cnthctl(val);
00038         break;
00039     case GENERIC_TIMER_REG_KCTL:
00040         write_cntkctl(val);
00041         break;
00042     case GENERIC_TIMER_REG_HYP_CTRL:
00043         write_cnthp_ctl(val);
00044         break;
00045     case GENERIC_TIMER_REG_HYP_TVAL:
00046         write_cnthp_tval(val);
00047         break;
00048     case GENERIC_TIMER_REG_PHYS_CTRL:
00049         write_cntp_ctl(val);
00050         break;
00051     case GENERIC_TIMER_REG_PHYS_TVAL:
00052         write_cntp_tval(val);
00053         break;
00054     case GENERIC_TIMER_REG_VIRT_CTRL:
00055         write_cntv_ctl(val);
00056         break;
00057     case GENERIC_TIMER_REG_VIRT_TVAL:
00058         write_cntv_tval(val);
00059         break;
00060     default:
00061         uart_print("Trying to write invalid generic-timer register\n\r");
00062         break;
00063     }
00064 
00065     isb();
00066 }
00067 
00068 static inline uint32_t generic_timer_reg_read(int reg)
00069 {
00070     uint32_t val;
00071 
00072     switch (reg) {
00073     case GENERIC_TIMER_REG_FREQ:
00074         val = read_cntfrq();
00075         break;
00076     case GENERIC_TIMER_REG_HCTL:
00077         val = read_cnthctl();
00078         break;
00079     case GENERIC_TIMER_REG_KCTL:
00080         val = read_cntkctl();
00081         break;
00082     case GENERIC_TIMER_REG_HYP_CTRL:
00083         val = read_cnthp_ctl();
00084         break;
00085     case GENERIC_TIMER_REG_HYP_TVAL:
00086         val = read_cnthp_tval();
00087         break;
00088     case GENERIC_TIMER_REG_PHYS_CTRL:
00089         val = read_cntp_ctl();
00090         break;
00091     case GENERIC_TIMER_REG_PHYS_TVAL:
00092         val = read_cntp_tval();
00093         break;
00094     case GENERIC_TIMER_REG_VIRT_CTRL:
00095         val = read_cntv_ctl();
00096         break;
00097     case GENERIC_TIMER_REG_VIRT_TVAL:
00098         val = read_cntv_tval();
00099         break;
00100     default:
00101         uart_print("Trying to read invalid generic-timer register\n\r");
00102         break;
00103     }
00104 
00105     return val;
00106 }
00107 
00108 static inline void generic_timer_reg_write64(int reg, uint64_t val)
00109 {
00110     switch (reg) {
00111     case GENERIC_TIMER_REG_HYP_CVAL:
00112         write_cnthp_cval(val);
00113         break;
00114     case GENERIC_TIMER_REG_PHYS_CVAL:
00115         write_cntp_cval(val);
00116         break;
00117     case GENERIC_TIMER_REG_VIRT_CVAL:
00118         write_cntv_cval(val);
00119         break;
00120     case GENERIC_TIMER_REG_VIRT_OFF:
00121         write_cntvoff(val);
00122         break;
00123     default:
00124         uart_print("Trying to write invalid generic-timer register\n\r");
00125         break;
00126     }
00127 
00128     isb();
00129 }
00130 
00131 static inline uint64_t generic_timer_reg_read64(int reg)
00132 {
00133     uint64_t val;
00134 
00135     switch (reg) {
00136     case GENERIC_TIMER_REG_HYP_CVAL:
00137         val = read_cnthp_cval();
00138         break;
00139     case GENERIC_TIMER_REG_PHYS_CVAL:
00140         val = read_cntp_tval();
00141         break;
00142     case GENERIC_TIMER_REG_VIRT_CVAL:
00143         val = read_cntv_cval();
00144         break;
00145     case GENERIC_TIMER_REG_VIRT_OFF:
00146         val = read_cntvoff();
00147         break;
00148     default:
00149         uart_print("Trying to read invalid generic-timer register\n\r");
00150         break;
00151     }
00152 
00153     return val;
00154 }
00155 #endif